1. Field of the Invention
This invention relates in general to the field of computer systems, and in particular, to an apparatus and method for processing short data streams using data prefetching.
2. Description of Related Art
Pipelined processing has been popular in computer and microprocessor architectures. Pipelining improves overall throughput by overlapping independent operational stages. There are three types of pipelining: instruction, data, and computational. An instruction pipeline involves several stages in executing instructions, e.g., fetch, decode, operand, execute, and write-back. Computational pipelines typically involve several stages of a computation process, such as steps in multiplication algortihms. Data pipelines involve any form of overlapping of segments of a data stream.
Problems associated with pipelined architectures are well known. Some examples of these problems include data dependences, branch conditions, and latencies. Data dependences and branch conditions are relevant in an instruction pipeline. In all types of pipeline architectures, however, the latency problem is particularly significant.
Pipeline latency refers to the start-up delay caused by the time it takes to fill up the pipe before concurrent operations can begin to take place. For a fixed pipeline length, the effect of pipeline latency depends on the length of the data stream to be processed. If the data stream is much longer than the pipeline latency, the delay is negligible. However, for short data streams, the pipeline latency becomes a dominant factor and creates performance bottleneck.
The problem is even more pronounced in applications where there is an initial period for fetching data before processing the data. Examples of such applications include 3-D graphic and image processing, video conferencing, and scientific visualization.
Therefore, there is a need in the technology for providing an efficient method to process short data streams using pipelining.